The present invention relates to the field of printed circuit boards and, more particularly, to the placement of electrical components on a circuit board and routing traces therebetween.
Printed circuit boards (PCBs) are commonly used in electronic devices for supporting and connecting electronic components such as application specific Integrated circuits (ASICs), processors, discrete components, sockets, connectors, and the like (collectively referred to herein as components). Each PCB includes a to circuit board having designated areas (i.e., footprints) on the surface of the circuit board for receiving the components. Such footprints may include vias or pads or other means for electrical coupling to leads of the components they receive. In addition, each PCB includes connection lines (i.e., traces) for connecting the components to one another.
Often, circuit boards contain multiple layers with traces running on one or more layers. Vias, which are conductive elements that extend through holes in the layers of a multi-layer circuit board, connect the components on the surface of the circuit board to traces running on layers other than the surface layer. In addition, vias connect portions of a trace that are routed on different circuit board layers. For example, assume a trace has two portions that together connect a first component and a second component and that the first portion is on a first Inner layer below the surface layer and the second portion Is on a second inner layer below the first inner layer. In this example, a first via connects the first component on the surface layer to the first portion, a second via connects the first portion to the second portion, and a third via connects the second portion to the second component on the surface layer.
Often it is desirable to Interconnect a group of components on a PCB, e.g., to connect each component within a group to each of the other components within the group. FIG. 4 depicts a circuit board 400, a group of four components 402a-d, and a plurality of traces 404a-f interconnecting each component within the group of four components. Conventionally, to interconnect a group of four components 402a-d, the Individual components are arranged to form a grid such that each component Is aligned with at least one other component in a first direction, e.g., along the X axis (horizontally), and at least one other component in a second direction perpendicular to the first direction, e.g., along the Y axis (along the Y axis). For example, a first component 402a is aligned with a second component 402b along the X axis and aligned with a third component 402c along the Y axis.
The traces 404a-f illustrated in FIG. 4 may be a single trace or may represent a signal buss, which generally contains 16 to 512 or more individual traces. The traces between aligned components (i.e., traces 404a, c, e, and f) may be formed using a circuit board 400 with a conventional number of layers and xe2x80x9cstandardxe2x80x9d vias, which extend through all the layers of the circuit board 400. Standard vias are relatively Inexpensive and easy to produce and, since they extend through the entire circuit board, allow complete testing of the PCB from a surface opposite the surface containing the components.
The traces between the diagonal components in FIG. 4 (i.e., traces 404b and 404d), however, result in a congested region 406 between the group of components 402a-d due to the high number of traces that cross toward the midpoint 408 between the components 402a-d. Routing the traces through this congested region 406 to form the necessary connections between diagonal components necessitates the use of unconventional routing techniques, a prohibitively large number of circuit board layers, xe2x80x9cburied vias,xe2x80x9d and/or xe2x80x9cblindxe2x80x9d vias. Buried vias and blind vias extend through one or more layers of the circuit board, but not through the entire circuit board. Burled and blind vias are relatively expensive and difficult to produce. In addition, since buried and blind vias do not extend through the entire circuit board, the PCB cannot be tested completely from the surface opposite the surface containing the components.
Accordingly, apparatus and methods are needed for positioning components and routing traces therebetween that reduce congestion and are not subject to the above-described limitations. The present Invention satisfies this need among others.
The present invention is an apparatus and method for positioning components on a circuit board and routing traces therebetween. The circuit board has two pairs of electrical component-receiving footprint and a plurality of traces interconnecting the footprints. The two pairs of electrical component-receiving footprints are spaced from one another in a first direction, wherein the footprints in each of the pairs are substantially aligned in a second direction substantially perpendicular to the first direction, and wherein at least one of the footprints in one of the pairs is offset from at least one of the footprints in the other of the pairs in both the first and second directions. The plurality of traces interconnect each of the footprints includes at least one trace connecting the offset footprints. The trace has a first portion extending from one of the offset footprints toward the other one of the offset footprints in substantially the first direction, a second portion extending from the other one of the offset footprints toward the one of said offset footprints in substantially the first direction, and a third portion extending between the first portion and the second portion in substantially the second direction.